1. Field of the Invention
The present invention relates to a memory system used in a portable telephone, a PDA (Personal Digital Assistant) or the like, and particularly, to a memory system that allows fast operation of a CPU (Central Processing Unit) or an MPU (Micro Processing Unit) while using an AND-type or NAND-type flash memory with a large capacity incapable of random access.
2. Description of the Background Art
In recent years, machines such as portable telephones, PDAs, information appliances and the like have become widespread. When a memory with a large capacity is required in such a machine for being adapted to i-mode, for transmission/reception of a digital camera image, for transmission/reception of moving images and the like, a flash memory with a large capacity is often connected to the machine.
FIG. 1 is a block diagram showing an example of a schematic configuration of a memory system in a conventional portable telephone. The portable telephone includes a CPU 104 performing general control of the portable telephone, a RAM/ROM 108 and an NOR-type flash memory 111 connected to an internal bus 103, a DRAM (Dynamic Random Access Memory) 110 connected to external buses 100 to 102, and a bus switch circuit 105 switching buses between external buses 100 to 102 and internal bus 103.
NOR-type flash memory 111 stores a program code executed by CPU 104. CPU 104 can access RAM/ROM 108 connected to internal bus 103 and DRAM 110 connected to external buses 100 to 102 at a high speed.
When a memory with a capacity much larger than that of NOR-type flash memory 111 is required, a memory system 112 is connected to external buses 100 to 102 in the portable telephone. Memory system 112 includes a control circuit 113 performing general control of memory system 112, and an AND-type or NAND-type flash memory 114 with a large capacity.
Flash memory 114 is capable of serial reading or serial writing of data sector by sector (one sector being, for example, 512 bytes or 1024 bytes) in synchronization with a serial clock, so that it is suitable for file storage.
Control circuit 113 has functions of generating a sector/column address of flash memory 114, performing serial/parallel bus conversion, and generating a serial clock.
When CPU 104 accesses flash memory 114 via external buses 100 to 102, address decoder 123 decodes an address output from CPU 104. Control circuit 113 receives the result of decoding by address decoder 123, interprets a command sent from CPU 104 via external buses 100 to 102, generates a required sector/column address, and accesses flash memory 114.
When CPU 104 reads data from flash memory 114, control circuit 113 converts serial data output from flash memory 114 into parallel data, and outputs the parallel data to external data bus 100 via a parallel bus. Moreover, when CPU 104 writes data into flash memory 114, control circuit 113 converts the parallel data output from CPU 104 into serial data, and outputs the serial data to flash memory 114 via a serial bus.
The data read from flash memory 114 is stored into RAM 108, DRAM 110 and the like, and can be accessed by CPU 104 at a high speed.
FIG. 2 is a block diagram showing another example of a schematic configuration of a memory system in the conventional portable telephone. The portable telephone is configured as in the portable telephone shown in FIG. 1, so that detailed description thereof will not be repeated.
A memory system 115 is formed by a card for file storage such as a compact flash (R) card or an ATA (AT Attachment) card, and includes a controller LSI (Large Scale Integrated circuit) 116 controlling the entire memory system, and an AND-type or NAND-type flash memory 114.
Controller LSI 116 has a function of generating a sector/column address of flash memory 114, a serial-parallel converting function, and a function of interpreting a command from CPU 104.
When CPU 104 accesses flash memory 114 via external buses 100 to 102, it issues a command indicating reading or writing of data to controller LSI 116. Controller LSI 116 interprets the command received from CPU 104, and controls flash memory 114 in accordance with the command.
FIG. 3 is a block diagram showing a further example of a schematic configuration of a memory system in the conventional portable telephone. The portable telephone is configured as in the portable telephone shown in FIG. 1, so that detailed description thereof will not be repeated.
A memory system 118 is formed by a card for file storage such as a memory stick of a serial bus type performing transmission/reception with serial data, a secure digital (SD) card, or a multimedia card (MMC), and includes a controller LSI 119 controlling the entire memory system and an AND-type or NAND-type flash memory 114.
Controller LSI 119 has a function of generating a sector/column address of flash memory 114, a function of interpreting a command from CPU 104 and the like.
When CPU 104 accesses flash memory 114 via external buses 100 to 102, it issues a command indicating reading or writing of data to controller LSI 119. An S/P (Serial/Parallel) bus conversion circuit 120 converts the command received from CPU 104 into serial data, and outputs the serial data to controller LSI 119.
Controller LSI 119 interprets the command of serial data received from S/P bus conversion circuit 120 and controls flash memory 114 in accordance with the command.
Moreover, a technique related to the above includes inventions disclosed in Japanese Patent Laying-Open No. 11-316716 and Japanese Patent Laying-Open No. 11-345194.
According to the memory control method disclosed in Japanese Patent Laying-Open No. 11-316716, data is transferred from a buffer memory to the flash ROM (Read Only Memory) by DMA (Direct Memory Access) transfer at writing the data into a flash ROM, to increase the speed of memory transfer.
Further, according to the portable telephone disclosed in Japanese Patent Laying-Open No. 11-345194, in response to an instruction sent by a CPU to a DSP (Digital Signal Processor) when a prescribed event occurs, the DSP performs DMA transfer of an application program on a rewritable external ROM such as a flash memory to an integrated RAM for the DSP to execute the application program, allowing correction/updating of the application program without the need for changing the DSP.
In the portable telephone shown in FIG. 1, control circuit 113 converts the serial data received from flash memory 114 via a serial bus into parallel data and outputs the parallel data onto a parallel bus, so that the transfer rate is determined by the rate of bus conversion, resulting in approximately a tenth the rate required by external buses 100 to 102 in general. Thus, memory system 112 directly connected to external buses 100 to 102 could not serve as a main memory of the portable telephone, causing a problem of lowered processing speed.
In addition, external buses 100 to 102 are occupied by data transfer during reading of data from flash memory 114, significantly lowering the bus efficiency and causing large overhead.
Moreover, in the portable telephone shown in FIG. 2, controller LSI 116 receives a command from CPU 104, interprets the command, and then converts the serial data received from flash memory 114 via a serial bus into parallel data to be output onto the parallel bus, causing a problem similar to that in the portable telephone shown in FIG. 1.
Further, in the portable telephone shown in FIG. 3, controller LSI 119 receives a command of serial data from S/P bus conversion circuit 120, interprets the command, and inputs the serial data from flash memory 114 via the serial bus. Thereafter, S/P bus conversion circuit 120 converts the serial data received from controller LSI 119 into parallel data and outputs the parallel data onto the parallel bus, causing a problem similar to that in the portable telephone shown in FIG. 1.
Moreover, the memory capacity within each of the portable telephones shown in FIGS. 1 to 3 may be increased without connection to memory system 112, 115 or 118, to accommodate increase of applications and the like. This, however, significantly increases the price compared to the case with an AND-type or NAND-type flash memory, and also increases the mounting area associated with the increase of the memory capacity.
Furthermore, according to the memory control method disclosed in Japanese Patent Laying-Open No. 11-316716, data is transferred from a buffer memory to a flash ROM by the DMA transfer, which however is not a technique for increasing the speed of an application.
In addition, according to the portable telephone disclosed in Japanese Patent Laying-Open No. 11-345194, the DSP is tightly coupled with the flash memory, so that access to the flash memory by the CPU is limited to a certain degree during the DMA transfer of data from the flash memory to the RAM in the DSP, also providing a limitation for enhancement of the processing speed of the portable telephone. Furthermore, while a randomly accessible flash memory is required as a precondition, the configuration above cannot achieve an increased capacity of a memory.
An object of the present invention is to provide a memory system that can be connected to a non-volatile memory with a large capacity while maintaining a processing speed of a system.
According to one aspect of the present invention, a memory system includes a non-volatile memory, a main memory connected to an external bus to which a processor is connected, a transfer control portion controlling direct memory access transfer between the non-volatile memory and the main memory, and a bus conversion portion performing conversion between parallel data and serial data between the non-volatile memory and the main memory.
The transfer control portion transfers data from the non-volatile memory that is converted into parallel data by the bus conversion portion to the main memory, eliminating the need for the processor downloading file data from the non-volatile memory to the main memory, allowing connection to a non-volatile memory with a large capacity without lowering of the processing speed of the system.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.